Commonly available Shift Register ICs (source) How do shift registers move data?.Some commonly available shift registers.How to design a 4-bit Parallel in Serial Out shift register (PISO)?.How to design a 4-bit Parallel in Parallel Out shift register (PIPO)?.How to design a 4-bit Serial In Parallel Out shift register (SIPO)?.How to design a 4-bit Serial In Serial Out shift register (SISO)?.The Arasan High Speed SPI – AHB IP Core has been widely used in different applications by major chip vendors. The Arasan High Speed SPI – AHB IP Core is an RTL design in Verilog that implements an SPI – AHB controller on an ASIC, or FPGA. The SPI controller consists of one SPI master and one SPI slave and it can be programmed by an AHB host to support the TI, Motorola, or National SPI protocol.

The Status and Interrupt Generator provides data transaction information to the AHB host processor that reflects the FIFOs and DMA states. A SPI clock frequency from 500 KHz to 50 MHz can be selected. A SPI Clock Generator is included to provide adjustable input clock to the SPI controller. The AHB master consists of a DMA controller to enhance the system performance. A 32-bit x 32-bit transmit FIFO and a 32- bit x 32-bit receive FIFO serve as the data buffer to coordinate data flows between the AHB and SPI interfaces. The AHB – SPI bridge performs either parallel-to-serial conversion or serial-to-parallel conversion with a maximum throughput of 50 Mbit/sec. Both AHB and SPI support master and slave modes. The controller can be used in applications such as flash memory card and digital camera. The SPI – AHB bridge enables an AHB host to access a serial device at high-speed through the SPI interface.

AHB, PCI or other custom specific buses can also be provided upon request. The I2S Controller IP supports a 32-bit parallel bus interface. The I2S Controller also includes interrupt support for reporting FIFO and other conditions. These two interfaces can be operated in two independent clock domains. The included transmit FIFO and receive FIFO handle data transfers between the I2S interface and application interface. DAC/ADC resolution is configurable from 8-bit to 32-bit. The I2S Controller IP supports 44.1KHz audio samplingrates.

The Bit Clock (BLCK) and Left and Right Clock (LRCK) provide synchronization for the transmit and receive data. Each channel can be programmed as an I2S master or an I2S slave. The controller’s I2S interface consists of one transmitter and one receiver. The Arasan I2S Controller IP Core provides a 32-bit parallel processor bus as the application interface. The I2S bus is used for connecting audio components such as speakers, DACs, or audio subsystems. The Arasan I2S Controller IP Core is a two-channel I2S serial audio controller compliant to the Philips* Inter-IC Sound specification.

8 bit parallel to serial converter ic